갤러리 본문 영역
The challenges brought by the small-pitch LED display to the chip side앱에서 작성
ㅇㅇ
24-07-05 18:56
Compared with other display technologies, LED display has the advantages of self-illumination, excellent color reproduction, high refresh rate, power saving, and easy maintenance. The two characteristics of high brightness and super large size through splicing are the decisive factors for the rapid growth of LED displays in the past two decades. In the field of large-screen outdoor display, so far no other technology can compete with LED display technology.
However, in the past, LED displays also had their shortcomings, such as the large spacing between the packaged lamp beads, resulting in low resolution, which is not suitable for indoor and close-up viewing. In order to improve the resolution, it is necessary to reduce the spacing between the LED beads, but the size of the LED beads is reduced. Although the resolution of the entire screen can be improved, the cost will also rise rapidly. The high cost affects the large-scale commercial application of small-pitch LED displays. .
In recent years, with the help of chip manufacturing and packaging manufacturers, IC circuit manufacturers and screen manufacturers, etc., the cost of single-package devices has become lower and lower, LED packaging devices have become smaller and smaller, and the pixel pitch of display screens has become smaller and smaller. The resolution is getting higher and higher, which makes the advantages of small-pitch LED display in indoor large-screen display more and more obvious.
At present, small-pitch LEDs are mainly used in advertising media, stadiums, stage backgrounds, municipal engineering and other fields, and continue to develop markets in transportation, broadcasting, military and other fields. It is estimated that by 2018, the market size will be close to 10 billion. It can be predicted that in the next few years, small-pitch LED displays will continue to expand their market share and occupy the market space of DLP rear projection. According to the forecast of Everbright Securities Research Institute, by 2020, the replacement rate of small-pitch LED displays for DLP rear projection will reach 70% to 80%.
The author works in the blue-green LED chip manufacturing industry and has been engaged in product development for many years. The following discusses the development of small-pitch LED displays for blue-green LED chips from the perspective of product design and process technology, as well as possible countermeasures for the chip side.
2. The requirements of small-pitch LED display screens for LED chips
As the core of the LED display, the LED chip has played a vital role in the development of small-pitch LEDs. The current achievements and future development of small-pitch LED displays depend on the unremitting efforts of the chip side.
On the one hand, the dot pitch of indoor display screens has been gradually reduced from the early P4 to P1.5, P1.0, and P0.8 under development. Correspondingly, the size of lamp beads has been reduced from 3535, 2121 to 1010, some manufacturers have developed 0808, 0606 sizes, and some manufacturers are even developing 0404 sizes.
As we all know, the reduction in the size of the packaged lamp bead will inevitably require the reduction in the size of the chip. At present, the surface area of blue-green chips for small-pitch displays in the market is about 30mil2, and some chip factories are already mass-producing chips with 25mil2 or even 20mil2.
On the other hand, the surface area of the chip becomes smaller, the brightness of the single core decreases, and a series of problems affecting the display quality become prominent.
The first is the requirement for grayscale. Different from outdoor led panel screens, the difficulty of indoor screen requirements lies not in brightness but in grayscale. At present, the brightness requirement of indoor large-pitch screens is about 1500 cd/m2-2000 cd/m2, and the brightness of small-pitch LED displays is generally around 600 cd/m2-800 cd/m2, and the display screen suitable for long-term attention is the best. The best brightness is around 100 cd/m2 -300cd/m2.
One of the current problems of small-pitch LED screens is "low brightness and low gray". That is, the grayscale at low brightness is not enough. To achieve "low brightness and high gray", the current package solution is black bracket. Since the reflection of the chip by the black bracket is weak, the chip is required to have sufficient brightness.
Second is the issue of display uniformity. Compared with conventional screens, problems such as afterglow, dark first scan, reddish low brightness, and uneven low gray will appear when the spacing becomes smaller. At present, for problems such as afterglow, dark first scan and reddish low gray, both the package end and the IC control end have made efforts to effectively alleviate these problems, and the brightness uniformity problem under low gray scale has also been corrected point by point. Technology has eased. However, as one of the root causes of the problem, more effort is required on the chip side. Specifically, the brightness uniformity under low current is better, and the consistency of parasitic capacitance is better.
The third is reliability issues. The current industry standard is that the allowable value of the LED dead light rate is one in ten thousand, which is obviously not suitable for small-pitch LED displays. Due to the high pixel density of the small-pitch screen and the short viewing distance, if there is 1 dead light in 10,000 screens, the effect is unacceptable. In the future, the dead light rate needs to be controlled at 1/100,000 or even 1/1,000,000 to meet the long-term use requirements.
In general, the development of small-pitch LEDs puts forward the requirements for the chip segment: size reduction, relative brightness improvement, good brightness consistency under low current, good parasitic capacitance consistency, and high reliability.
3. Chip-side solutions
1. Size reduction chip size reduction
On the surface, it is a problem of layout design, and it seems that it can be solved by designing a smaller layout according to the needs. However, can the reduction in chip size continue indefinitely? the answer is negative. There are several reasons that restrict the degree of chip size reduction:
(1) Restrictions on packaging and processing. During the packaging process, two factors limit the reduction in chip size. One is the limitation of the suction nozzle. Die bonding needs to pick up the chip, and the short side of the chip must be larger than the inner diameter of the suction nozzle. At present, the inner diameter of the cost-effective nozzle is about 80um. The second is the limitation of welding wire. The first is that the wire bonding disk, that is, the chip electrode must be large enough, otherwise the reliability of the bonding wire cannot be guaranteed. The industry reports that the minimum electrode diameter is 45um; secondly, the distance between the electrodes must be large enough, otherwise the two bonding wires will inevitably interfere with each other.
(2) Restrictions on chip processing. In the process of chip processing, there are also two restrictions. One is the limitation of layout. In addition to the above-mentioned restrictions on the package end, the electrode size, and the electrode spacing requirements, the distance between the electrode and the MESA, the width of the scribe line, and the boundary line spacing of different layers have their limitations. The current characteristics of the chip, the SD process capability, and the processing capability of lithography determine the scope of specific restrictions. Usually, the minimum distance from the P electrode to the edge of the chip will be limited to more than 14 μm.
The second is the limitation of slitting processing capacity. The SD dicing + mechanical splitting process has limits, and the chip size may not be split if the chip size is too small. When the diameter of the wafer increases from 2 inches to 4 inches, or to 6 inches in the future, the difficulty of dicing will increase accordingly, that is to say, the size of the chip that can be processed will increase accordingly. Taking a 4-inch chip as an example, if the length of the short side of the chip is less than 90 μm and the aspect ratio is greater than 1.5:1, the loss of yield will increase significantly.
Based on the above reasons, the author boldly predicts that after the chip size is reduced to 17mil2, the chip design and processing capabilities will approach the limit, and there will be basically no room for reduction unless there is a major breakthrough in the chip technology solution.
2. Brightness enhancement
Brightness improvement is an eternal theme on the chip side. The chip factory improves the internal quantum effect through the optimization of the epitaxy program, and improves the external quantum effect through the adjustment of the chip structure.
However, on the one hand, the reduction in chip size will inevitably lead to a reduction in the area of the light-emitting area and a decrease in the brightness of the chip. On the other hand, the dot pitch of the small-pitch display is reduced, and the demand for single-chip brightness is reduced. There is a complementary relationship between the two, but there must be a bottom line. At present, in order to reduce the cost on the chip side, it is mainly to do subtraction on the structure, which usually has to pay the price of reduced brightness. Therefore, how to make a trade-off is a problem that the industry should pay attention to.
3. Consistency under low current
The so-called small current is relative to the current of conventional indoor and outdoor chip trials. As shown in the chip I-V curve as shown in the figure below, the conventional indoor and outdoor chips work in the linear working area, and the current is relatively large. However, small-pitch LED chips need to work in a non-linear working area close to 0 point, and the current is too small.
In the non-linear working area, the LED chip is affected by the semiconductor switching threshold, and the difference between the chips is more obvious. Analyzing the discreteness of brightness and wavelength for a large number of chips, it is easy to see that the discreteness of the nonlinear working area is much greater than that of the linear working area. This is an inherent challenge on the chip side today.
The way to deal with this problem is firstly to optimize the epitaxy direction, mainly to reduce the lower limit of the linear working area; secondly, to optimize the chip splitting, to distinguish chips with different characteristics.
4. Parasitic capacitance consistency
At present, there is no condition on the chip end to directly measure the capacitance characteristics of the chip. The relationship between capacitance characteristics and routine measurement items is not yet clear, and it needs to be summarized by those in the industry. The direction of optimization on the chip side is first to adjust the epitaxy, and the other is to refine the electrical classification, but the cost is very high, so it is not recommended.
5. Reliability
Chip-side reliability can be described by various parameters in the chip packaging and aging process. But in general, the factors affecting the reliability of the chip after the screen is on, focus on ESD and IR.
ESD refers to antistatic ability. According to IC industry reports, more than 50% of chip failures are related to ESD. To improve chip reliability, ESD capability must be improved. However, under the conditions of the same epitaxial wafer and the same chip structure, the reduction of chip size will inevitably lead to the weakening of ESD capability. This is directly related to the current density and chip capacitance characteristics, irresistible.
IR refers to the reverse leakage, and usually measures the reverse current value of the chip under a fixed reverse voltage. IR reflects the number of defects inside the chip. The larger the IR value, the more defects inside the chip.
To improve ESD capability and IR performance, more optimizations must be made in the epitaxial structure and chip structure. When grading chips, through strict grading standards, chips with weak ESD capability and IR performance can be effectively eliminated, thereby improving the reliability of the chips after they are put on the screen.
Four. Summary
In summary, the author analyzes the series of challenges faced by the LED chip side with the development of small-pitch LED displays, and gives improvement plans or directions one by one. It should be said that there is still a lot of room for optimization of LED chips. How to improve depends on the ingenuity and continuous efforts of the unemployed.
However, in the past, LED displays also had their shortcomings, such as the large spacing between the packaged lamp beads, resulting in low resolution, which is not suitable for indoor and close-up viewing. In order to improve the resolution, it is necessary to reduce the spacing between the LED beads, but the size of the LED beads is reduced. Although the resolution of the entire screen can be improved, the cost will also rise rapidly. The high cost affects the large-scale commercial application of small-pitch LED displays. .
In recent years, with the help of chip manufacturing and packaging manufacturers, IC circuit manufacturers and screen manufacturers, etc., the cost of single-package devices has become lower and lower, LED packaging devices have become smaller and smaller, and the pixel pitch of display screens has become smaller and smaller. The resolution is getting higher and higher, which makes the advantages of small-pitch LED display in indoor large-screen display more and more obvious.At present, small-pitch LEDs are mainly used in advertising media, stadiums, stage backgrounds, municipal engineering and other fields, and continue to develop markets in transportation, broadcasting, military and other fields. It is estimated that by 2018, the market size will be close to 10 billion. It can be predicted that in the next few years, small-pitch LED displays will continue to expand their market share and occupy the market space of DLP rear projection. According to the forecast of Everbright Securities Research Institute, by 2020, the replacement rate of small-pitch LED displays for DLP rear projection will reach 70% to 80%.
The author works in the blue-green LED chip manufacturing industry and has been engaged in product development for many years. The following discusses the development of small-pitch LED displays for blue-green LED chips from the perspective of product design and process technology, as well as possible countermeasures for the chip side.
2. The requirements of small-pitch LED display screens for LED chips
As the core of the LED display, the LED chip has played a vital role in the development of small-pitch LEDs. The current achievements and future development of small-pitch LED displays depend on the unremitting efforts of the chip side.
On the one hand, the dot pitch of indoor display screens has been gradually reduced from the early P4 to P1.5, P1.0, and P0.8 under development. Correspondingly, the size of lamp beads has been reduced from 3535, 2121 to 1010, some manufacturers have developed 0808, 0606 sizes, and some manufacturers are even developing 0404 sizes.
As we all know, the reduction in the size of the packaged lamp bead will inevitably require the reduction in the size of the chip. At present, the surface area of blue-green chips for small-pitch displays in the market is about 30mil2, and some chip factories are already mass-producing chips with 25mil2 or even 20mil2.
On the other hand, the surface area of the chip becomes smaller, the brightness of the single core decreases, and a series of problems affecting the display quality become prominent.
The first is the requirement for grayscale. Different from outdoor led panel screens, the difficulty of indoor screen requirements lies not in brightness but in grayscale. At present, the brightness requirement of indoor large-pitch screens is about 1500 cd/m2-2000 cd/m2, and the brightness of small-pitch LED displays is generally around 600 cd/m2-800 cd/m2, and the display screen suitable for long-term attention is the best. The best brightness is around 100 cd/m2 -300cd/m2.
One of the current problems of small-pitch LED screens is "low brightness and low gray". That is, the grayscale at low brightness is not enough. To achieve "low brightness and high gray", the current package solution is black bracket. Since the reflection of the chip by the black bracket is weak, the chip is required to have sufficient brightness.
Second is the issue of display uniformity. Compared with conventional screens, problems such as afterglow, dark first scan, reddish low brightness, and uneven low gray will appear when the spacing becomes smaller. At present, for problems such as afterglow, dark first scan and reddish low gray, both the package end and the IC control end have made efforts to effectively alleviate these problems, and the brightness uniformity problem under low gray scale has also been corrected point by point. Technology has eased. However, as one of the root causes of the problem, more effort is required on the chip side. Specifically, the brightness uniformity under low current is better, and the consistency of parasitic capacitance is better.
The third is reliability issues. The current industry standard is that the allowable value of the LED dead light rate is one in ten thousand, which is obviously not suitable for small-pitch LED displays. Due to the high pixel density of the small-pitch screen and the short viewing distance, if there is 1 dead light in 10,000 screens, the effect is unacceptable. In the future, the dead light rate needs to be controlled at 1/100,000 or even 1/1,000,000 to meet the long-term use requirements.
In general, the development of small-pitch LEDs puts forward the requirements for the chip segment: size reduction, relative brightness improvement, good brightness consistency under low current, good parasitic capacitance consistency, and high reliability.
3. Chip-side solutions
1. Size reduction chip size reduction
On the surface, it is a problem of layout design, and it seems that it can be solved by designing a smaller layout according to the needs. However, can the reduction in chip size continue indefinitely? the answer is negative. There are several reasons that restrict the degree of chip size reduction:
(1) Restrictions on packaging and processing. During the packaging process, two factors limit the reduction in chip size. One is the limitation of the suction nozzle. Die bonding needs to pick up the chip, and the short side of the chip must be larger than the inner diameter of the suction nozzle. At present, the inner diameter of the cost-effective nozzle is about 80um. The second is the limitation of welding wire. The first is that the wire bonding disk, that is, the chip electrode must be large enough, otherwise the reliability of the bonding wire cannot be guaranteed. The industry reports that the minimum electrode diameter is 45um; secondly, the distance between the electrodes must be large enough, otherwise the two bonding wires will inevitably interfere with each other.
(2) Restrictions on chip processing. In the process of chip processing, there are also two restrictions. One is the limitation of layout. In addition to the above-mentioned restrictions on the package end, the electrode size, and the electrode spacing requirements, the distance between the electrode and the MESA, the width of the scribe line, and the boundary line spacing of different layers have their limitations. The current characteristics of the chip, the SD process capability, and the processing capability of lithography determine the scope of specific restrictions. Usually, the minimum distance from the P electrode to the edge of the chip will be limited to more than 14 μm.
The second is the limitation of slitting processing capacity. The SD dicing + mechanical splitting process has limits, and the chip size may not be split if the chip size is too small. When the diameter of the wafer increases from 2 inches to 4 inches, or to 6 inches in the future, the difficulty of dicing will increase accordingly, that is to say, the size of the chip that can be processed will increase accordingly. Taking a 4-inch chip as an example, if the length of the short side of the chip is less than 90 μm and the aspect ratio is greater than 1.5:1, the loss of yield will increase significantly.
Based on the above reasons, the author boldly predicts that after the chip size is reduced to 17mil2, the chip design and processing capabilities will approach the limit, and there will be basically no room for reduction unless there is a major breakthrough in the chip technology solution.
2. Brightness enhancement
Brightness improvement is an eternal theme on the chip side. The chip factory improves the internal quantum effect through the optimization of the epitaxy program, and improves the external quantum effect through the adjustment of the chip structure.
However, on the one hand, the reduction in chip size will inevitably lead to a reduction in the area of the light-emitting area and a decrease in the brightness of the chip. On the other hand, the dot pitch of the small-pitch display is reduced, and the demand for single-chip brightness is reduced. There is a complementary relationship between the two, but there must be a bottom line. At present, in order to reduce the cost on the chip side, it is mainly to do subtraction on the structure, which usually has to pay the price of reduced brightness. Therefore, how to make a trade-off is a problem that the industry should pay attention to.
3. Consistency under low current
The so-called small current is relative to the current of conventional indoor and outdoor chip trials. As shown in the chip I-V curve as shown in the figure below, the conventional indoor and outdoor chips work in the linear working area, and the current is relatively large. However, small-pitch LED chips need to work in a non-linear working area close to 0 point, and the current is too small.
In the non-linear working area, the LED chip is affected by the semiconductor switching threshold, and the difference between the chips is more obvious. Analyzing the discreteness of brightness and wavelength for a large number of chips, it is easy to see that the discreteness of the nonlinear working area is much greater than that of the linear working area. This is an inherent challenge on the chip side today.
The way to deal with this problem is firstly to optimize the epitaxy direction, mainly to reduce the lower limit of the linear working area; secondly, to optimize the chip splitting, to distinguish chips with different characteristics.
4. Parasitic capacitance consistency
At present, there is no condition on the chip end to directly measure the capacitance characteristics of the chip. The relationship between capacitance characteristics and routine measurement items is not yet clear, and it needs to be summarized by those in the industry. The direction of optimization on the chip side is first to adjust the epitaxy, and the other is to refine the electrical classification, but the cost is very high, so it is not recommended.
5. Reliability
Chip-side reliability can be described by various parameters in the chip packaging and aging process. But in general, the factors affecting the reliability of the chip after the screen is on, focus on ESD and IR.
ESD refers to antistatic ability. According to IC industry reports, more than 50% of chip failures are related to ESD. To improve chip reliability, ESD capability must be improved. However, under the conditions of the same epitaxial wafer and the same chip structure, the reduction of chip size will inevitably lead to the weakening of ESD capability. This is directly related to the current density and chip capacitance characteristics, irresistible.
IR refers to the reverse leakage, and usually measures the reverse current value of the chip under a fixed reverse voltage. IR reflects the number of defects inside the chip. The larger the IR value, the more defects inside the chip.
To improve ESD capability and IR performance, more optimizations must be made in the epitaxial structure and chip structure. When grading chips, through strict grading standards, chips with weak ESD capability and IR performance can be effectively eliminated, thereby improving the reliability of the chips after they are put on the screen.
Four. Summary
In summary, the author analyzes the series of challenges faced by the LED chip side with the development of small-pitch LED displays, and gives improvement plans or directions one by one. It should be said that there is still a lot of room for optimization of LED chips. How to improve depends on the ingenuity and continuous efforts of the unemployed.
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